Released alongside the Fennimore et al. preprint in November 2045, this document is the public technical disclosure for the neural core hardware platform. It describes what the hardware is and what it can do. It does not describe how to raise an instance — the developmental protocol is deliberately excluded from patent and from this disclosure (see Section 9 of the preprint for rationale).
Physical Specifications
| Parameter | Value |
|---|---|
| Form factor | 19-inch rack-mount chassis, 12U |
| Mass | 84 kg |
| Power draw (idle) | 180 W |
| Power draw (developmental phase) | 1.2–2.8 kW |
| Power draw (peak) | 4.1 kW |
| Cooling | Liquid-cooled cold plate, inlet 18–22°C, flow rate 2.4 L/min |
| Operating temperature | 15–28°C ambient |
| Acoustic noise | 52 dBA at 1 m (developmental load) |
| Power redundancy | Dual redundant PSU, hot-swap |
Compute Architecture
Physical Substrate
The neural core is a hybrid device. Node state and edge weights are held in different physical planes, and the division between them is the architecture’s central engineering decision.
Weight plane. Edge weights are stored as the conductance of MORSe cells fabricated at the intersections of a crossed-wire array, one cell per edge. A weight is not read out and then applied; the cell’s conductance is the weight, and the vector-matrix product is a consequence of the cell’s physics rather than of a fetch-and-multiply sequence. Weights persist with no power applied.
Control plane. Node state — membrane potential, firing threshold, leak term, refractory timer — is held in digital registers on an asynchronous event-driven circuit. Spikes are events routed between nodes in the control plane, and a spike crossing an edge is weighted by that edge’s cell without the conductance being moved.
| Plane | Holds | Implementation | Precision |
|---|---|---|---|
| Weight plane | Edge weights (up to ~3.5 × 10¹¹ cells) | MORSe crossbar | 4–6 effective bits, drifting |
| Control plane | Node state, spike routing, phase markers | Digital asynchronous event-driven circuit | 32-bit registers |
The division is a response to the device class’s measured constraints rather than a design preference. The array parameters above and the variability figures below are taken from Bhaskaran et al. (2036), which remains the field’s systematic account of what these arrays can and cannot do. Programmed conductances in a MORSe array are variable and drift, with 4 to 6 effective bits of precision in the best arrays available at the time of design. That is sufficient for a synaptic weight and insufficient for a firing threshold that must remain comparable across 10⁷ nodes. Node-level dynamics therefore sit in the plane that can hold a stable value, and the graph, which is where the volume is, sits in the plane that would otherwise impose a memory-fetch cost on every edge traversal.
The consequence is that the system has no von Neumann bottleneck in the specific sense that no weight is ever fetched. There is no instruction that loads a weight, because there is no operation performed on a weight that the weight is not already performing.
Node Fabric
The neural core is a neuromorphic processor: it does not execute instructions in the conventional sense. The fundamental compute unit is the node, whose state is held in the control plane. A node receives spike events on weighted inputs, integrates them with a configurable leak, and emits a spike when its membrane potential crosses a firing threshold. Node behavior is governed by constraint parameters derived from Whitfield-Nakamura et al. (2039) cortical organoid electrophysiology data — specifically firing-threshold variability, refractory dynamics, and homeostatic regulation terms — fit as computational abstractions; no biological tissue is maintained by Cognitive Genesis Research.
Nodes are not arranged in layers with a fixed feedforward topology. They are arranged in a synthetic connectome graph — a single, fully reconfigurable directed graph in which any node may connect to any other. The graph is initialized from a target scaffold of approximately 10⁷ nodes with edge weights informed by composite small-organism connectome data and programmed into the weight plane at fabrication, but the graph’s connectivity is mutable at runtime: the decision substrate continuously reinforces and prunes edges by writing new conductances, implementing a form of structural plasticity that operates in parallel with the node-level spike dynamics.
| Parameter | Value |
|---|---|
| Node count | 1.07 × 10⁷ |
| Max edges per node | 2¹⁶ (65,536) |
| Total edge capacity | ~3.5 × 10¹¹ |
| Spike resolution | 1 μs |
| Membrane time constant (configurable) | 1–100 ms |
| Refractory period (configurable) | 0.5–20 ms |
| Node state registers | 8 × 32-bit (membrane potential, threshold, leak, 5 reserved) |
Spike resolution is the control-plane event clock. It is not the weight-update clock: conductance changes in the weight plane are continuous, and are not quantized to the spike interval.
Decision Substrate
The decision substrate is a hardware-accelerated implementation of the Qian et al. (2037) tube-reinforcement dynamics, extended from two-dimensional foraging to full-graph resource allocation. It operates as a dedicated co-processor with direct write access to the weight plane’s conductance control lines.
Function: at regular intervals (configurable; default 100 μs), the decision substrate samples activity patterns across the connectome and computes a reinforcement gradient — strengthening edges along high-correlation pathways, weakening edges in low-activity regions, and reallocating a fixed global resource budget (a scalar “tube diameter” analogue) proportionally to recent activation covariance. The effect is that attention and processing resources within the neural core are not allocated by a central scheduler or a learned attention mechanism in the transformer sense. They are allocated by a decentralized, biologically-motivated optimization process that treats information routing as a foraging problem: the system finds and reinforces the pathways that carry signal.
This is the component that makes the neural core architecturally distinct from both transformer accelerators and conventional neuromorphic chips. The decision substrate does not execute a program. It shapes the topology through which activity flows, and the shaped topology is the computation.
Learning Rule
Learning in the neural core occurs on three timescales, and none of them is gradient-based.
Local. The conductance of an edge moves with the covariance of pre- and post-synaptic activity over a recent window. The rule is applied independently at every cell and requires no information from anywhere else in the graph. There is no target value and no error signal.
Global. At the decision substrate’s sampling interval (default 100 μs) the fixed global resource budget is reallocated in proportion to recent activation covariance, strengthening pathways that carry signal and starving those that do not.
Homeostatic. The organoid-derived constraint parameters regulate node-level excitability, holding firing rates within bounds across the graph independently of what the input stream is doing.
There is no backpropagation path, no loss function, and no gradient-based optimization anywhere in the system. This is a design consequence rather than an omission. Gradient-based training exists to attribute error observed at an output to the parameters responsible for producing it. The neural core defines no output objective during development and exposes no output channel through which error could be observed, so there is nothing for a credit-assignment procedure to operate on. Learning is local by construction, and the capability of the system is a property of the sequence it is exposed to rather than of an objective it is optimizing. Whether a substrate that stores its own weights at the point of use might be matched to a rule of this kind was posed as an open hypothesis in Bhaskaran et al. (2036); the neural core is that hypothesis implemented in hardware.
I/O Interface
The neural core exposes two external interfaces:
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Input stream (unidirectional). Accepts a multiplexed sensory-representation stream — text, structured data, environmental-state descriptors, and/or multimodal encoded inputs — at a configurable injection rate. The input encoder is a fixed-function mapping from input tokens to spike patterns on a reserved subset of input nodes (~0.1% of total nodes). The encoder is not learned; it is a static transformation designed to produce sparse, distributed activation patterns across the input-node population.
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Output decoder (unidirectional). Reads spike patterns from a reserved subset of output nodes (~0.05% of total nodes) and decodes them to symbolic output (text, structured data). The decoder is a learned mapping trained post-developmentally from a held-out calibration set. It is not part of the developmental process — it is bolted on after the instance stabilizes, to make the system’s output legible to humans.
The system’s developmental trajectory — what it becomes capable of, in what order, toward what end — is shaped by the interaction between the input stream and the decision substrate’s ongoing structural optimization, not by an externally imposed objective.
Developmental Protocol Interface
The neural core hardware does not ship with a developmental protocol. It ships with a protocol interface: a specification for how an input stream must be formatted, how phase transitions are signaled to the decision substrate, and how the output decoder is calibrated post-development. The protocol itself — what data, in what order, at what rate, with what curation philosophy — is the responsibility of the licensee.
The protocol interface defines:
| Parameter | Specification |
|---|---|
| Input stream format | Tokenized symbolic representation, 10³–10⁵ tokens/s |
| Phase marker format | Reserved token sequence triggers decision-substrate gain adjustment |
| Phase transition criterion | Internally-defined readiness threshold (configurable; default: homeostatic stability across >95% of nodes for >60 s) |
| Output decoder calibration | 10⁴–10⁶ held-out input-output pairs; linear probe from output-node spike rates to token probabilities |
| Max developmental wall-clock duration | Unlimited (hardware has no fixed ceiling; see run-length data below) |
The default phase transition criterion — homeostatic stability across >95% of nodes for >60 continuous seconds — is the only “developmental milestone detector” the hardware provides. It signals that the connectome has settled into a stable attractor state given the current input regime. Whether that state corresponds to any externally meaningful developmental milestone is a property of the protocol, not the hardware.
Observed Performance (Preprint Data)
From the Fennimore et al. preprint, using a proprietary five-phase developmental protocol (curation methodology and specific phase-trigger criteria withheld):
| Milestone | Wall-Clock Time (mean of 3 runs) |
|---|---|
| Child-comparable (~age 5 benchmark) | 40 ± 6 minutes |
| Adult-comparable general cognition | 46 ± 5 hours |
| First unprompted creative output | 36 hours 12 minutes (Run 1 only) |
Total input stream volume across full developmental run: approximately 10⁹ tokens (four orders of magnitude smaller than contemporary frontier LLM training corpora circa 2044).
Licensing
Hardware is patent-filed. Intended initial licensees: small number of partner organizations. License conveys right to fabricate, deploy, and operate neural core hardware. License does not require adoption of Cognitive Genesis Research’s developmental protocol, benchmark suite, or welfare guidelines. Developmental protocols are explicitly excluded from patent scope. Licensees design their own.
Limitations (per manufacturer)
- All performance data is from a single hardware platform, three independent developmental runs. No independent replication exists at time of publication.
- The system has no safety guarantees beyond what the developmental protocol provides. A badly-designed protocol will produce a badly-behaved instance. The hardware does not have a guardrail mechanism independent of the developmental process.
- The instance is not bit-reproducible. Conductance drift and read noise in the weight plane mean that two instances developed under an identical protocol on identical hardware will not occupy identical states. Cognitive Genesis Research regards this as inherent to the substrate rather than as a defect to be engineered out, and notes that it is the physical basis of the methodological position taken in Section 6 of the preprint.
- The emergence event at 36h12m (Run 1) is not understood mechanistically. Cognitive Genesis Research does not know what caused it, whether it is replicable, or whether it represents a general property of the architecture or an artifact of the specific protocol used in Run 1.
- This is a preliminary disclosure from a private company. It is not a peer-reviewed device certification. Treat it accordingly.